At the receiver end there is a need for symbol synchronization in order to successfully recover the transmitted signal. The purpose of the timing recovery loop is to obtain symbol synchronization. To achieve symbol synchronization the parameter that should be determined are

• Sampling frequency.
• Sampling phase

Locking the sampling frequency requires estimating the symbol period so that samples can be taken at the correct rate . Generally, sampling frequency should be known in advance to the receiver, but oscillator drift may introduce deviations from the known symbol rate.
The other quantity to be determined is sampling phase. Locking the sampling phase involves determining the correct time within a symbol period to take a sample. Real-world symbol pulse shapes have a peak in the center of the symbol period. Sampling the symbol at this peak results in the best signal-to-noise-ratio and will ideally eliminate interference from other symbols. This type of interference is known as ISI.
The timing recovery loop alters the sampling frequency and sampling phase to sample the signal at the peaks. Thus timing recovery loop samples the signal at highest SNR for error free recovery of the transmitted signal. Figure below shows the basic receiver involving symbol recovery block

There are innumerable algorithms that have been proposed for symbol recovery. But the basic goal of timing recovery algorithms is

• Estimation of the timing error
• Correction of the timing error using VCO in PLL or using interpolation or by adjusting the taps in the receiver filter

Timing Recovery Loop
The key to timing recovery loop is sampling at the correct instant to avoid ISI which will further assist in estimating the transmitted symbol correctly. In the receiver architecture the output of the matched filter should be sampled at the correct instant i.e. at the symbols peak periodically. The timing recovery loop adjusts the sampling phase and sampling frequency to sample the matched filter output at its peak. Thus with timing recovery block operating properly high SNR level output can be achieved optimizing the receivers performance.
Figure below shows the principle involved in digital timing recovery block

The A/D block converts analog signal into digital signal. A/D converter performance is dictated by the sampling rate of A/D block and its dynamic range.
The interpolator helps in adjusting the timing frequency and phase by generating the intermediate samples between the samples generated by the A/D block. The interpolator inserts N-1 zeros in between data sample. The up-sampled signal is passed through the LPF to remove the aliases. Thus after the interpolation and filtering the sampling rate of the signal effectively increases by N. The TED (timing error detector) block may use various algorithms deshe interp;aoRcribed below to generate the sampling timing error. The control signal for the interpolator is generated by the loop filter based on the input from TED. The loop filter can be based on second order loop filter.

TED Algorithms
Few of the widely used TED algorithms are described below
Early-late gate algorithm
The output of the matched filter is fed to the timing recovery block to sample this waveform at the peaks in order to obtain the best performance in the presence of noise. If the timing recovery circuit is not sampling at the peaks then, we say that it is either sampling early or late. The task of timing recovery block is to find the peaks without assistance from the user.

The early late recovery arbitrarily selects a sample, called the on-time sample, from the matched filter output. The sample from the time-index one greater than that of the on-time sample is the late sample and the sample from the time-index one less than that of the on-time sample is the early sample.
The on-time sample is the output of the timing recovery block will be used to decide the data bit sent. To achieve the best performance in the presence of noise, it adjusts the timing of on-time samples to coincide with peaks in the waveform. It does this by changing the number of time-indices between on-time samples.

This timing recovery algorithm generates its error by using samples that are early and late compared to the ideal sampling point. The generation of the error requires at least three samples per symbol. The method of generating the error is illustrated in Figure . Note that the early and late samples are at different amplitudes. This difference in amplitude is used to derive an error for the timing recovery loop. Once the timing recovery loop converges, the early and late samples will be at equal amplitudes. The sample to be used for later processing is the sample that lies in the middle of the early and late samples.
One drawback of the early-late gate algorithm is that it requires at least three samples per symbol. Thus, it is impractical for systems with high data rates.
Mueller and Muller Algorithm
The Mueller and Muller algorithm only requires one sample per symbol. The Mueller and Mueller algorithm only requires one sample per symbol.

The error is computed using the following equation
en = (yn )*(yn-1') - (yn-1 )*(yn')

yn = samples from current symbol
yn = samples from previous symbol
yn'= decision taken by the slicer based on received samples from current symbol
yn-1' = decision taken by the slicer based on received samples from current symbol.
One drawback of this algorithm is that it is sensitive to carrier offsets, and thus carrier recovery must be performed prior to the Mueller and Muller timing recovery

Gardner Algorithm
This algorithm uses two samples per symbol. The error for gardener algorithm is calculated using following equation
en = (yn - yn –2 ) * yn -1
where spacing between yn and yn –2 is T second yn and yn –1 is T/2 second.

Figure below illustrates how the sign of gardner error can be used to determine the whether the sampling is correct. Note that gardner error is most useful on symbol transition, The gardner error is relatively small when the current and previous samples have same polarity. The timing recovery loop typically locks first, therefore simplifying the task of carrier recovery.
Gardener timing illustration
Figure below shows the illustration of Early Late Gate Algorithm
Correct Timing: error(en) = (-1-1)*0

Timing is Late :error(en) = (-0.75-0.75)* - 0.25 = 0.375

Timing is early:error(en) = (-0.75-0.75) * 0.25 = -0.375

References
{1} Digital Communication by John G Proakis
{2} F. M. Gardner, “A BPSK/QPSK Timing Error Detector for Sampled Receivers,” IEEE Transactions on
Communications,
{3}A New Interpolated Symbol Timing Recovery Method Xiong Liu and Alan N. Willson, Jr.

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