HSC welcomes all external visitors to this site, especially students and members of the academic community. Please use the comments box at the bottom of each page to record any comments or suggestions for improvement. Design constraints of Pipelines architectures:

Definition: A pipeline is a chain of Processing Units(PU) which may operate in blocked-for-input i.e. synchronous(SYN) mode or in asynchronous(ASN) mode. The pipeline offers only one input(I) and one output(O) point.

Design constraints:

1. Number of cores
2. Efficiency of the Inter Processing Unit Communciation. (IPC)
3. Scheduling(SHD) of Processing Blocks.
4. Synchronicity of PUs.
5. I/O at PUs (not part of the pipeline, but important)

Non Issues:

1. Loss of info during IPC, since IPC is assumed to operate over a reliable Link Layer.
2. File I/O is assumed to be buffered and does not create a choke point at the I or O points.
3. Every thing else: Process structure, OS, File System, VM access, User input, Input/Output formats.

Theoritical Background:

1. Petri Net Graph can be used to model a mesh of computing nodes, a very limited version of it can be used to model a Pipeline.
2. A queue of queues (single server, single client) can be used to model the pipeline to compute average waiting times, so as to bound the IPC delays.

Thoughts: How about using the concept of nonlinear pipelines to match pattern. It is already done as part of the finite automata based pattern matching, but can it be speeded up??

References

1. http://www.cise.ufl.edu/research/ParallelPatterns/PatternLanguage/AlgorithmStructure/Pipeline.htm
2. http://www.cise.ufl.edu/research/ParallelPatterns/PatternLanguage/AlgorithmStructure/AsynchComp.htm

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